1. Field of the Invention
The present invention generally relates to a data transferring system that transfers data and an electronic apparatus that provides the data transferring system.
2. Description of the Related Art
As a high speed serial interface, an interface called PCI Express (peripheral component interconnect express, registered trademark) being a successor of PCI is proposed (for example, refer to Non-Patent Document 1).
In PCI Express, in order to make the power consumption low, link states of L0, L0s, L1, and L2 are defined. The link state L0 is a normal mode and the power consumption is lowered corresponding to the change of the link state from L0s to L2. Details of the link states are explained below.
FIG. 15 is a timing chart showing a control example of power source management by the link states. In the link state L2 shown in FIG. 15 (a), a power saving mode is established in a ms order and power source management is executed by software control, and the period of the power saving mode is shown in “L2”. In the link state L1 shown in FIG. 15(b), the power saving mode is established in a μs order and the power source management is executed by hardware control, and the period of the power saving mode is shown in “L1”. In the link state L0s shown in FIG. 15(c), the power saving mode is established in a ns order and the power source management is executed by hardware control, and the period of the power saving mode is shown in “L0s”. 
Shifting to each of the power saving modes (link states) L0s, L1, and L2 from the link state L0 requires time, in addition, time is required to return to the link state L0 from the power saving modes (link states) L0s, L1, and L2. In the link state L0s which needs the shortest time to return to the link state L0 and the returning time is 16 ns to 4 μs.
[Non-Patent Document 1] Outline of the PCI Express Standard, Interface July 2003, written by Takashi Satomi
However, as described above, in both cases of the shifting to each of the power saving modes from the link state L0 and returning to the link state L0 from each of the power saving modes, time is required. Therefore, even in the link state L0s in which the returning time to the link state L0 is the shortest, when the shifting and the returning are frequently repeated, power saving cannot be executed in the empty time during the shifting and the returning. Consequently, sufficient power saving cannot be executed.